Description
Entreprise :
Electronics multinational based in Lausanne with presence in different countries.
Description du poste :
You will report to the Engineering manager and will have the opportunity to be a driving force of the Physical design team. Your day-to-day work will entail the following:
* Reading and analyzing the system requirements and architecture requirement documents.
* Plan for functional verification activities for a given subsystem/functionality.
* Physical design.
* Verification environment development and maintenance in SystemVerilog/UVM/SystemC/C++.
* Project milestones and deliverable planning with external partners.
* Organize work and deliverable between skills, internal and external teams.
* Opportunities for mentoring and training the next generation of hardware engineers.
Description du profil :
We are particularly looking for engineers with at least 10 years of experience in:
* RTL Coding
* Physical design
* Experienced in:
*
- SystemVerilog/VHDL
- SystemC/C++
* Some previous experience in Firmware based programing / verification is a good to have.
* Good level of English, both written and spoken is mandatory. French is an asset.